FIG. 35 is a circuit diagram showing a CAM cell which is disclosed in IEEE Journal of Solid State Circuits vol. sc-7, No. 5, Oct. 1972, pp. 364-369. A first conducting terminal of a first insulated gate field effect transistor M.sub.W1 (supposed to be an n-MOS transistor in this case) is connected to a first bit line BL, and its control terminal (gate) is connected to a word line WL. Similarly, a first conducting terminal of a second n-MOS transistor M.sub.W2 is connected to a second bit line BL, and its gate is connected to the word line WL.
A first conducting terminal of a third n-MOS transistor M.sub.S1 is connected to the first bit line BL, and its gate is connected to a second conducting terminal of the first transistor M.sub.W1. Similarly, a first conducting terminal of a fourth n-MOS transistor M.sub.S2 is connected to the second bit line BL, and its gate is connected to a second conducting terminal of the second transistor M.sub.W2.
A first conducting terminal of a fifth n-MOS transistor M.sub.D is commonly connected to respective second conducting terminals of the third and fourth transistors M.sub.S1 and M.sub.S2, while its gate and second conducting terminal are commonly connected to a match line ML.
In the conventional CAM cell structured in the aforementioned manner, the first bit line BL is brought into an "H" level and the second bit line BL is brought into an "L" level since the memory cell is formed by the n-MOS transistors. The first transistor M.sub.W1 is turned on if the word line WL enters an "H" level at this time, and hence positive electric charges are stored in the gate of the third transistor M.sub.S1 from the first bit line BL which is at the "H" level, whereby the third transistor M.sub.S1 is also turned on. On the other hand, the second transistor M.sub.W2 is also turned on in response to the "H" level of the word line WL, while the fourth transistor M.sub.S2 enters an off state since the gate of the fourth transistor M.sub.S2 is connected to the second bit line BL which is at the "L" level. Writing of information (data) is completed when the word line WL is brought into an "L" level in this state. It is assumed here that this storage state is data logic "1".
In order to retrieve stored data, the match line ML is precharged at an "H" level, and data to be referred to is supplied to the bit line pair BL and BL. Supposing that "1" is supplied as reference data, the first bit line BL is brought into an "H" level and the second bit line BL is brought into an "L" level. At this time, the fifth transistor M.sub.D is turned on since the match line ML is at the "H" level, while the match line ML is connected with the first bit line BL and cut off from the second bit line BL since the third and fourth transistors M.sub.S1 and M.sub.S2 are in on and off states respectively in the aforementioned storage state "1". However, the "H" level of the match line ML is maintained since the first bit line BL is at the "H" level. Namely, it can be recognized that the stored data matches the reference data since the precharge level "H" of the match line ML is maintained.
When "0" is supplied as the reference data, on the other hand, the first bit line BL is brought into an "L" level and the second bit line BL is brought into an "H" level. At this time, charges are extracted from the match line ML being at the "H" level to the first bit line BL being at the "L" level through the fifth transistor M.sub.D and the third transistor M.sub.S1 which are in on states, whereby the match line ML, which is in a floating state, enters an "L" level. Namely, it can be recognized that the stored data mismatches the reference data since the precharge level "H" of the match line ML is changed to "L".
FIG. 36 is a circuit diagram showing a CAM cell which is disclosed in Japanese Patent Laying-Open Gazette No. 31091/1988. In this CAM cell, a first conducting terminal of a first non-volatile memory transistor M.sub.F1 (floating gate avalanche transistor, for example) is connected to a word line WL/match line ML, while its control gate is connected to a first bit line BL and its second conducting terminal is grounded. Symmetrically, a first conducting terminal of a second non-volatile memory transistor M.sub.F2 is connected to the word line WL/match line ML and its control gate is connected to a second bit line BL, while its second conducting terminal is grounded.
Supposing that the first bit line BL is brought into an "H" level and the second bit line BL is brought into an "L" level while the word line WL is brought into an "H" level in the CAM cell shown in FIG. 36, electrons caused by avalanche breakdown in the first floating gate avalanche transistor M.sub.F1 are attracted toward the control gate which is at an "H" level, whereby the electrons are injected into the floating gate. Consequently, threshold voltage V.sub.TH of the first floating gate avalanche transistor M.sub.F1 goes high. On the other hand, the control gate of the second floating gate avalanche transistor M.sub.F2 is at an "L" level, and hence no electron injection into the floating gate is caused and its threshold voltage V.sub.TH is maintained in a low state. Thus, information can be written in a pair of non-volatile memory transistors M.sub.F1 and M.sub.F2.
In order to refer to such written data, the match line ML is precharged at an "H" level, while the first bit line BL is brought into an "H" level and the second bit line BL is brought into an "L" level, for example. At this time, the first non-volatile memory transistor M.sub.F1 will not conduct since its threshold voltage V.sub.TH is high. Further, the second non-volatile memory transistor M.sub.F2, whose threshold voltage V.sub.TH remains in a low state, will not conduct since the potential of its control gate is at an "L" level. That is, both the first and second non-volatile memory transistors are in non-conducting states, so that the "H" level of the match line ML is maintained. Thus, it is recognized that the content reference data supplied to the bit line pair BL and BL matches the stored data.
If the first bit line BL is brought into an "L" level and the second bit line BL is brought into an "H" level to the contrary, the second non-volatile memory transistor M.sub.F2 enters a conducting state. Therefore, charges are extracted from the match line ML through the second non-volatile memory transistor M.sub.F2, and the match line ML is brought into an "L" level. Thus, it is recognized that the content reference data supplied to the bit line pair BL and BL mismatches the stored data.
FIG. 37 is a block diagram showing an example of a conventional CAM system. Referring to this figure, a plurality of CAM cells CC are arrayed in the form of a matrix along row and column directions. FIG. 37 illustrates CAM cells CC which are in a four-by-four array. Word lines WL are commonly connected to the CAM cells of the respective rows. First ends of the four word lines WL are connected to a decoder DC. This decoder DC selects one of the word lines WL on the basis of inputted address data A0 and A1. Bit lines BL and BL are commonly connected to the CAM cells CC of the respective columns. Respective first ends of the bit lines BL and BL are connected to an input/output circuit IO1. Further, match lines ML are commonly connected to the CAM cells CC of the respective rows. Match/mismatch detection circuits M are provided on terminal ends of the respective match lines ML. These match/mismatch detection circuits M are adapted to detect match/mismatch between reference data on the bit lines BL and BL and data stored/held in the CAM cells CC on the respective rows. Further, selectors SL are provided on second ends of the respective word lines WL. These selectors SL are circuits which are adapted to select either the corresponding word lines WL or outputs from the match/mismatch detection circuits M.
On the other hand, RAM cells RC are provided in a four-by-four array, in one-to-one correspondence to the aforementioned CAM cells CC. In the array formed by these RAM cells RC, word lines WL are commonly connected to the RAM cells RC of the respective rows and bit lines BL and BL are commonly connected to the RAM cells RC of the respective columns similarly to the aforementioned array of the CAM cells. Outputs of the aforementioned respective selectors SL are supplied to corresponding word lines WL in the array of the RAM cells respectively. First ends of the respective bit lines BL and BL are connected to another input/output circuit IO2.
FIG. 38 is a circuit diagram showing the detail of a portion 1R enclosed by dotted lines in FIG. 37. As shown in the figure, one CAM cell includes a transfer transistor TW1 which is connected to a word line WL and a bit line BL, another transfer transistor TW2 which is connected to the word line and another bit line BL, a memory cell MC which is arranged between these transfer transistors TW1 and TW2 and structured by connecting two inverters in an inverse-parallel manner, and a comparison circuit CON which is formed by four transistors Tr1 to Tr4. All of the transistors employed in FIG. 38 are n-channel MOS transistors.
Operation of the prior art example shown in FIGS. 37 and 38 is now described with reference to a timing chart shown in FIG. 39.
First, operation for writing information in the memory cell MC of the CAM cell CC is described. When the bit line BL is brought into an "H" level and the bit line BL is brought into an "H" level while the word line WL is brought into an "H" level and thereafter returned to an "L" level, a node a is maintained at an "H" level and another node b is maintained at an "L" level. This state is called a state in which "1" is written in the memory cell MC. In this state, the transistor Tr1 is off and the transistor Tr2 is on. On the other hand, when the bit line BL is brought into an "L" level and the bit line BL is brought into an "H" level while the word line WL is brought into an "H" level and thereafter returned to an "L" level, the node a is maintained at an "L" level and the node b is maintained at an "H" level. This state is called a state in which "0" is written in the memory cell MC. In this state, the transistor Tr1 is on and the transistor Tr2 is off.
Then, operation for referring to storage data in each CAM cell CC is described. In the following description, it is assumed that "1" is stored/held in the memory cell MC of the CAM cell CC which is referred to. First, a control signal .phi. of an "H" level is supplied to the gate of a precharge transistor Tp shown in FIG. 38 by a prescribed period, so that the precharge transistor Tp is turned on to precharge the match line ML. Then, information to be referred to is inputted in the bit lines BL and BL. Supposing that "0" is supplied as this reference information (i.e., supposing that an "L" level is supplied to the bit line BL and an "H" level is supplied to the bit line BL), the transistor Tr3 is turned off and the transistor Tr4 is turned on. Thus, precharges of the match line ML are extracted through the transistors Tr2 and Tr4 to the ground, which serves as a reference potential source (refer to FIG. 39). Supposing that "1" is supplied to the bit lines BL and BL as reference information (i.e., supposing that an "H" level is supplied to the bit line BL and an "L" level is supplied to the bit line BL), on the other hand, the transistor Tr3 is turned on and the transistor Tr4 is turned off. Supposing that storage data of the memory cells MC of other CAM cells CC in the same row also match the reference data, therefore, the potential at the match line ML is maintained and match information is supplied to a corresponding word line WL on the RAM cell RC side through a driver D. In response to this, previously set storage data are read from the respective RAM cells RC belonging to the corresponding word lines WL and outputted to the exterior through the input/output circuit IO2.
As hereinabove described, the potentials of the memory cells MC are forced to the ground potential when reference data supplied through the bit lines BL and BL, while the same are maintained at the precharge potential when the former match the latter to the contrary. This operation also applies to the case where "0" is stored/held in the memory cells of the CAM cells CC to be referred to.
In the CAM cell shown in FIG. 35, it is necessary to perform rewriting (refreshment) since charges are stored in the gates of the insulated gate field effect transistors to hold the storage data, while there is such a problem that the storage data are lost when power is cut.
On the other hand, the storage are held even if power is cut in the CAM cell shown in FIG. 36, while the data stored in the memory cell cannot be directly read out from the bit line pair. That is, there is such a problem that the CAM cell shown in FIG. 36 cannot be used as a RAM cell (random access memory cell).
Further, the conventional CAM cell system will not recognize matching unless matching is attained in all bits of the same row since, if a bit of a CAM cell which mismatches reference information is included in a row, the potential of the match line ML is discharged to the ground potential through the said CAM cell. Thus, there is such a problem that it cannot be applied to a system (such as an associative system, for example) which has such a degree of redundance that it recognizes attainment of matching as a whole if the number of mismatching bits included in the same row is not more than a prescribed number.